View CY62148ESL-55ZAXI_4822122.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62148ESL MoBL(R)
4-Mbit (512K x 8) Static RAM
Features

Functional Description
The CY62148ESL is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Very high speed: 55 ns Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V Ultra low standby power Typical standby current: 1 A Maximum standby current: 7 A Ultra low active power Typical active current: 2 mA at f = 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 32-pin STSOP package

Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE WE OE
INPUT BUFFER ROW DECODER
IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6
512K x 8 ARRAY
COLUMN DECODER
POWER DOWN
IO7
A13 A14
A15
A16
A17
Cypress Semiconductor Corporation Document #: 001-50045 Rev. **
*
198 Champion Court
A18
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 21, 2009
[+] Feedback
CY62148ESL MoBL(R)
Pin Configuration
Figure 1. 32-Pin STSOP (Top View)
A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
STSOP Top View
(not to scale)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3
Product Portfolio
Power Dissipation Product Range VCC Range (V) [1] Speed (ns) Operating ICC, (mA) f = 1 MHz Typ CY62148ESL Industrial 2.2V to 3.6V and 4.5V to 5.5V 55 2
[2]
f = fmax Typ [2] 15 Max 20
Standby, ISB2 (A) Typ [2] 1 Max 7
Max 2.5
Notes 1. Data sheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
Document #: 001-50045 Rev. **
Page 2 of 10
[+] Feedback
CY62148ESL MoBL(R)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied .............................................. 55C to +125C Supply Voltage to Ground Potential ...........................................................-0.5V to 6.0V DC Voltage Applied to Outputs in High-Z State [3, 4] ..........................................-0.5V to 6.0V DC Input Voltage [3, 4] .......................................-0.5V to 6.0V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA
Operating Range
Device CY62148ESL Range Industrial Ambient Temperature VCC[5]
-40C to +85C 2.2V to 3.6V, and 4.5V to 5.5V
Electrical Characteristics
Over the Operating Range 55 ns Parameter VOH Description Output HIGH Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VOL Output LOW Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VIH Input HIGH Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VIL
[6]
Test Conditions IOH = -0.1 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA IOL = 2.1 mA
Min 2.0 2.4 2.4
Typ [2]
Max
Unit V
0.4 0.4 0.4 1.8 2.2 2.2 -0.3 -0.3 -0.5 -1 -1 15 2 1 VCC + 0.3 VCC + 0.3 VCC + 0.5 0.4 0.6 0.6 +1 +1 20 2.5 7
V
V
Input LOW Voltage
2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5
V
IIX IOZ ICC ISB1
Input Leakage Current
GND < VI < VCC f = fmax = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA, CMOS levels
A A mA A
Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current
Automatic CE Power CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Down Current -- CMOS f = fmax (Address and Data Only), f = 0 (OE and WE), Inputs VCC = VCC(max) Automatic CE Power CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Down Current -- CMOS f = 0, VCC = VCC(max) Inputs
ISB2
1
7
A
Notes 3. VIL(min) = -2.0V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 6. Under DC conditions the device meets a VIL of 0.8V (for VCC range of 2.7V to 3.6V and 4.5V to 5.5V) and 0.6V (for VCC range of 2.2V to 2.7V). However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. Refer to AN13470 for details.
Document #: 001-50045 Rev. **
Page 3 of 10
[+] Feedback
CY62148ESL MoBL(R)
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC GND Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still Air, soldered on a 3 x 4.5 inch, two layer printed circuit board STSOP 49.02 14.07 Unit C/W C/W
Equivalent to:
THEVENIN EQUIVALENT
RTH OUTPUT Parameters R1 R2 RTH VTH 2.50V 16667 15385 8000 1.20 3.0V 1103 1554 645 1.75 V 5.0V 1800 990 639 1.77 Unit V
Document #: 001-50045 Rev. **
Page 4 of 10
[+] Feedback
CY62148ESL MoBL(R)
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR [7] tR [8] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V VCC = 1.5V 0 tRC Conditions Min 1.5 1 7 Typ [2] Max Unit V A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
CE
Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document #: 001-50045 Rev. **
Page 5 of 10
[+] Feedback
CY62148ESL MoBL(R)
Switching Characteristics
Over the Operating Range [9] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[12]
Description
55 ns Min Max
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z
[10] [10, 11]
55 55 10 55 25 5 20 10 20 0 55
ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z CE LOW to Low Z
[10] [10, 11]
CE HIGH to High Z
CE LOW to Power Up CE HIGH to Power Up
Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z [10, 11]
[10]
55 40 40 0 0 40 25 0 20 10
ns ns ns ns ns ns ns ns ns ns
WE HIGH to Low Z
Notes 9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-50045 Rev. **
Page 6 of 10
[+] Feedback
CY62148ESL MoBL(R)
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled) [14, 15]
ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [16, 17]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA IO NOTE 18 tHZOE
Notes 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycles. 15. Address valid before or similar to CE transition LOW. 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 18. During this period, the IOs are in output state. Do not apply input signals.
tHD
DATA VALID
Document #: 001-50045 Rev. **
Page 7 of 10
[+] Feedback
CY62148ESL MoBL(R)
Switching Waveforms
(continued) Figure 6. Write Cycle No. 2 (CE Controlled) [16, 17]
tWC
ADDRESS tSCE tSA tAW tPWE WE tSD DATA IO DATA VALID tHD tHA
CE
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [17]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA IO NOTE 18 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Truth Table
CE H L L L WE X H H L OE X L H X High Z Data Out High Z Data in Inputs/Outputs Mode Deselect/Power Down Read Output Disabled Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Document #: 001-50045 Rev. **
Page 8 of 10
[+] Feedback
CY62148ESL MoBL(R)
Ordering Information
Speed (ns) 55 Ordering Code CY62148ESL-55ZAXI Package Diagram Package Type Operating Range Industrial
51-85094 32-Pin STSOP (Pb-Free)
Package Diagram
Figure 8. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094
51-85094-*D
Document #: 001-50045 Rev. **
Page 9 of 10
[+] Feedback
CY62148ESL MoBL(R)
Document History Page
Document Title: CY62148ESL MoBL(R) 4-Mbit (512K x 8) Static RAM Document Number: 001-50045 Rev. ** ECN No. 2612938 Orig. of Change VKN/PYRS Submission Date 01/21/09 New data sheet Description of Change
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
PSoC Solutions
General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
(c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-50045 Rev. **
Revised January 21, 2009
Page 10 of 10
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY62148ESL-55ZAXI

	To Download CY62148ESL-55ZAXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .